An ASIC Analog Neuromorphic Computer for Evolvable Hardware Applications

Aims: This paper presents a design for a custom Application-Specific-Integrated-Circuit (ASIC) VLSI continuous time recurrent neural network computer suitable for use in Evolvable Hardware (EH) applications.
Study Design: Extensive testing of a fabricated device will be used to demonstrate that the designed and fabricated neural chip possesses excellent behavioral congruence to the differential equation and ASIC hardware forms of neural networks programmed into the chip.
Place and Duration of Study: Department of Computer Science and Engineering, Wright State University, between 2009 and 2012.
Methodology: The presented ASIC neural chip has been designed with specific concentration on the CMOS sub-threshold design concepts. This CMOS sub-threshold design forms the basis for underlying neural computation and also the current-mode Digital-to-Analog Converter (DAC) that can be used to program neuron configurations. The proposed designed has been developed to be immune to any faults introduced thru fabrication, at least to the extent that is non-detrimental to underlying neural behavior.
Results: Ten separate intrinsic CTRNN learning runs were conducted on the fabricated chips. Each test was conducted on a separate fabricated chip to assess intrinsic to extrinsic transferability across individual instantiations of the device. Further, as mentioned earlier, a secondary set of tests were conducted that involved performing intrinsic match analysis for 15 (separate) extrinsically learnt CTRNN configurations to test extrinsic to intrinsic transferability. Based on the comparison metrics computed between the simulated and the fabricated chip, it has been demonstrated that the observed worst case average mismatch across all computed outputs of the four neuron CTRNNs is about seven percent on amplitude with near perfect matching for slope and frequency.
Conclusion: Extensive testing of a fabricated device has been used to demonstrate that the analog computer possesses excellent behavioral congruence to the differential equation and ASIC hardware forms of neural networks are programmed into the chip. The major advantage of choosing the proposed CTRNNs chip for EH applications is that one can easily transition between model and circuit form no matter how the circuit was evolved. In this paper, we demonstrated quite clearly that the barrier is either non-existent or very slight by having designed, fabricated, and tested an actual VLSI chip in the application that one would expect to be most difficult -- evolution in hardware and modeling in differential equation form.